DDR5 Explained – Why is it so EXPENSIVE? + XMP 3.0 Explained!
If you’ve been following the launch of Intel’s new Alder Lake CPUs, the new 12th gen chips, you’ll likely have heard about DDR5 – and just how painfully expensive it is. In this video I want to cover what’s actually new with DDR5, including the new XMP 3.0 spec which is actually a massive change from the XMP 2.0 we are all used to, and what makes these things so damn expensive.
Taking a look at a DDR5 module, you can see just how different it is from DDR… wait, no sorry this is a DDR4 module.. Ah right yeah THIS is the DDR5 one. Ok puns aside, you’d be forgiven for mistaking one for the other. I mean, they have the exact same number of pins, 288 specifically, although that doesn’t mean they are physically identical. Despite also sharing the same curved board design too, the notch that is slightly off centre to block the module from being installed in the wrong orientation has been moved. Only by a few millimeters, but it’s enough to mean you can’t install DDR4 in a DDR5 board, or vice versa.
Ok, so they changed the slot so we can’t use the old stuff in new boards… but why? What’s actually new? Remarkably, quite a lot! The biggest physical change is how the modules get their power. With DDR4, the motherboard supplies the modules with the exact amount of power they need, which for DDR4 is 1.2V as standard, or sometimes up to 1.35V for overclocked high speed kits. That’s pretty much the way it’s always been done, and to be honest it makes sense. Have one well built regulator to convert power from your power supply into the right level for the memory all at once, keep it in one place and highly efficient. The problem? Noise. The more copper you have between where that power outputs, and where it’s received, the more interference and noise can get at it.
But Andrew, it’s DC power, it’s a flat line! How can DC be “noisy”? Well, take a look. Here’s what the 5V on your USB ports actually looks like. That’s hardly a flat line, in fact, it’s varying by as much as 100mV, which doesn’t sound like much but when you are dealing with sensitive data in volatile memory and you are trying to achieve around 5,000,000,000 transfers per second, noise like this would make that impossible. Now to make it clear this isn’t what a motherboard’s memory power circuit would produce, but the principle is the same. The longer the line, the more other lines nearby will induce noise, the more radio frequencies can interfere, the noisier it gets.
The solution? Move the regulators onto the modules! Every DDR5 module will have one of these little voltage regulators, called a PMIC or power management integrated circuit. This means the modules are supplied with a regular power rail, specifically 12V for the module and 3.3V for the PMIC controller, and the power lines are now much, much shorter. This allows for more stable power to the memory chips themselves, allowing them to run faster with good stability. There are downsides to moving the regulator onto the module, specifically a reduction in efficiency as there are now regulators on each module doing their own thing rather than one well built one on the motherboard, which means increased heat output, and cost as you now have more components and significantly more complex PCB designs to accommodate the new controllers and other changes.
One thing I want to note quickly is something Intel mentioned in their Blueprint presentation, which is that there are two kinds of the PMIC controllers, overclockable ones and non-overclockable ones. The latter are set to 1.1V by default, although they should still allow you to set them to up to around 1.4V, likely through XMP or JEDEC profiles. The overclockable kind is something you have to specifically purchase, it’s physically different hardware, and so far I haven’t seen anyone advertising that feature so I would assume most modules on sale right now are the ‘locked’ kind.
Something else that’s pretty drastically changed is how the data is sent to your CPU. Modern CPUs are “64bit” – meaning they use up to 64 bit memory addresses, instructions and data like integers. Rather obviously then, your RAM has to be able to send those 64 bits to your CPU, and with how fast your CPU runs it’s best to send all of those bits at the same time. So, DDR4 does just that, it has one 64 bit wide connection to the CPU. Perfect! Except, it’s not. Not every piece of data or instruction is actually 64 bits wide. I mean in C# unless you specify a number as a “long”, a regular “int” is only 32 bits, so the RAM has to fill those extra 32 bits with wasted data before it can send it. That takes time, meaning the memory latency increases, and can mean your CPU has to sit idle just waiting for the data to come through.
So, what does DDR5 do? It splits that bus in two. DDR5 has 2 32 bit connections to the CPU, which can operate independently, or together. That means if a 32 bit int comes along, it’ll be fired through one bus without having to wait for the other to fill up with useless data, but if a 64 bit long drops by, it can send half over one and half over the other. On top of that, the burst buffer size – the queue of ready-to-go data – is now double that of DDR4 at 16 instead of 8, and technically speaking that is 16 per 32 bit bus but you can’t just add those together. This doesn’t count as dual channel, and you’ll still want to run multiple sticks of memory to get the best performance.
One of the most talked about features of the DDR5 ICs themselves is the introduction of “on-die ECC”. I should make it clear that this is not the same as ‘proper’ ECC, and it doesn’t mean every DDR5 module is now an ECC module. This doesn’t do any transmission error checking at all, hence the name “on-die”. What it does is instead of storing just the data, it stores the data AND 8 parity bits – a parity bit is basically like the result of an equation that you can use to know if something has gone wrong and sometimes even correct it. A single parity bit is often just storing whether the number of 1s and 0s is odd or even, so if any one bit flips by accident you’ll know that piece of data has been corrupted. The 8 parity bits here allow for actual correction though, on a single bit flip.
So, at a basic level, if you have a store an integer like 420, that would be written as 0001 1010 0100 in binary, but say by accident the second 0 flipped to a 1, well that number now reads 1444 which is significantly different to our original number, but thanks to those parity bits, the RAM can work out that the bit has flipped and correct it before it has a chance to break anything. This is completely transparent to you the user though, it happens automatically, and is a welcomed addition!
Now, that’s what’s new on the inside, but much like every new version of DDR, the timings and frequencies are changing too. As is the trend, the frequencies are going up, and sadly so are the timings. Intel’s maximum supported DDR5 frequency on their Alder Lake chips is 4800MT/s, up from 3200MT/s on DDR4. That’s a healthy improvement for sure, but the catch is the CAS latency, or how many RAM cycles it takes to return data, as that’s going from between CL12 to CL18, to more like CL34 to CL40, as in instead of taking 12 cycles to return data, it’ll now take 34. That means for certain workloads, it’s quite likely that DDR4 will actually be faster than DDR5 at least for now until the modules can reduce timings and increase the frequencies.
Speaking of timings and frequencies, let’s talk about XMP 3.0. XMP, or extreme memory profile, is a feature Intel developed back in 2007, which is basically profiles built into the module itself that the manufacturer has tested and validated to be stable on that kit. That means all you have to do is enable the profile and all of the timings, voltages and frequencies get automatically applied. XMP 2.0 comes with two onboard, hard coded profiles which can’t be renamed or saved over with your own custom settings. XMP 3.0 then, has 3 “locked” profiles from the memory manufacturer, AND 2 rewritable profiles you can save your own settings to – plus you can now attach custom names to each profile making it easy to know which is which. For example the manufacturer can include a ‘base’ profile, a ‘frequency’ optimised profile, and a ‘timings’ optimised profile, then you can save your own settings too.
So, why is DDR5 so damn expensive? Well, the new voltage regulators on every module definitely adds cost and the new larger XMP chip for storing those extra profiles including overwritable ones – at least for the modules that support XMP – both add to the cost of the modules long term. In the short term, the “early adopters tax”, basically purchasing these before they are being manufactured at a large enough scale that costs come down, isn’t helping and worse the global chip shortage and shipping madness means chip manufacturers are running completely at capacity and will be for the foreseeable future. That means you can expect DDR5 to remain potentially significantly more expensive for a fair while yet.
