The ONE Company That Makes ALL Our Chips…

Believe it or not, only one company in the entire world makes basically all of our chips – and it’s not tsmc, Intel or Samsung. This mysterious four letter company have a complete monopoly on the chip fabrication industry, and their latest design only pushes that monopoly further – and yet, they’re owned by their own customers. Their most recent machines are larger than a double decker bus, but can spit out 185 350mm wafers per hour, 24/7,365 days a year. This is this history of ASML. To understand how we got to warehouse sized single machines, we first need to understand how chips have been made throughout the last half-century of production. 

Semiconductor manufacturing, and transistors in particular which are the foundation of all integrated circuits, dates back to the late 1940s – surprisingly recent, isn’t it! Three guys at Bell Labs (because of course it was bell labs, they seem to have either accidentally or purposefully created the basis for everything we use today), William Shockley, Walter Brattain and John Bardeen created the first transistor. It wasn’t what you’d call “micro”, but it worked, and proved the concept. Unsurprisingly, another group at Bell labs made another (accidental) discovery. They accidentally grew a layer of silicone dioxide across a silicon wafer, which they quickly worked out you could use that as a mask to imprint designs in the silicon below. Just so you have an idea, silicon can be doped to be either “p type” or “n type”, and if you sandwich a bit of p or n between two of the opposite types, you create a channel, and therefore a transistor. This style of flat transistor is called a ‘planar’ transistor, since it’s all on one plane. And if you take that, and you’re either Robert Noyce of Fairchild or Jack Kilby of Texas Instruments in 1958, you might realise that you can put all that together to create integrated circuits and spawn the industry we now rely on. Amazingly the two of them actually independently invented the integrated circuit around the same time. The idea was pretty simple, chain multiple transistors together to create functional logic. These designs were pretty simple by modern standards, and we’re still talking near human eye visible feature size too. 

One key thing I mentioned in there was the silicon wafers – the big expensive discs that the designs get etched into – although to begin with they weren’t all that big. In 1960, when the first ICs were being built, you’d be looking at just a one inch wafer. You can’t fit many chips onto that one! The way those wafers are made is really cool too. Basically you melt down pure silicon, introduce a seed crystal into the molten silicon and basically draw a big semiconducting sausage called a boule up. That boule is then sliced into discs, polished to be perfectly flat, and sent off to be patterned. The disc sizes have gradually increased over the years. 1969 saw 2 inch wafers, which were 275 micrometres thick, 1972 brought 3 inch at 375 micrometres thick, and by 1976 they settled on metric sizing with “4 inch” 100mm wafers, then “4.9 inch” 125mm in 81, 150mm “6 inch” in 83, 200mm “8 inch” in 92 and 300mm “12 inch” in 99. There has been a proposed 450mm wafer standard for nearly two decades now, but due to the wafers being expected to cost quadruple that of a 300mm wafer, and that no fabrication machines currently support 450mm wafers the machine cost would go up considerably too, despite not actually cutting production costs all that much, so development of 450mm wafers seems to be dead in the water. 

So you’ve got your wafer, what do you actually put on it? Well initially as I said the designs were relatively simple, and importantly the designs all basically use just one of the two MOSFET types – MOSFET stands for metal oxide semiconductor field effect transistor by the way – specifically n-type. That was known as NMOS logic, and was the preeminent design choice. It wasn’t exactly ideal though, limiting circuit designs and often having pretty poor power efficiency as there’s still a bit of current leakage even in the off state, so Frank Wanlass of Fairchild developed a phrase us PC nerds know well (for a weird reason, actually), a design process called CMOS. You likely know that word thanks to the “CMOS Battery” in your PC, which is what we call the BIOS chip battery, but CMOS is actually the chip design. Complimentary metal oxide semiconductor designs use complimentary transistors to create logic – ie both types of transistor. The trick here is that because one of the two transistors will always be off when the input signal is the same, the power consumption drops and you get better noise immunity. CMOS slowly became the standard, and functionally all chip designs are now CMOS. Even things like camera sensors are CMOS sensors!

But like, how do you actually put those designs onto the wafer? Well it turns out we’ve been doing it the same way for the last half-decade and a bit – photolithography. The process is actually remarkably simple. You apply a coating to the wafer, then using a mask you selectively harden the coating in the areas you want to keep or remove, then etch the unprotected area away. The modern multi-layer method is slightly different, as you first deposit a thin layer of fresh silicon on top, then apply the resist – the coating – by spin-coating it. You stick the wafer on a turntable and pour on the liquid resist coating and spin the disc to evenly distribute the resist. You pre-bake it to get it stable, then you can use your mask and some ultraviolet light to selectively harden normally the areas you want to etch away. Then you use developer solution to wash away the hardened areas, leaving the silicon layer below open. You can then use chemical etching to strip away that silicon, effectively cutting your chip design into the wafer. You’ll do what’s called ion implantation to dope the different regions to create that p or n type area, do any metal or polycrystalline silicon deposition (the metal oxide part of MOSFET), and then you’ll then use resist stripper to clean the rest of the resist off, add a layer of silicon dioxide in and flatten it, then repeat for however many layers you have, then etch the silicon dioxide away, and hey-presto you’ve got a design etched into your wafer. 

So if the process has remained functionally the same for the last 60 years, what has actually changed to let us go from a 20 micrometre feature size in 1968, to 2 nanometre nodes today? Well just to be pedantic, especially in the last decade or so the process node doesn’t match the actual feature size anymore, but in short there’s two main changes, FinFET and the light source used for the photolithography. You might have heard the term FinFET before, likely mostly from Intel as their absolutely mental naming scheme for their process nodes included the term, even opting for “SuperFET” at one point, before reverting back to numbers (albeit nonsensical numbers, but still). FitFet basically means that instead of the gate being just placed on top of the channel, the channel is actually a thin blade – a fin, if you will – and the gate wraps around it entirely. That means you get much better control of the transistor with lower leakage, and you can essentially chain multiple fins together to control current capacity and switching characteristics. All modern CPUs and GPUs use FinFETs instead of planar transistors – or at least similar concepts anyway.

As for the light sources, that’s actually really interesting. Originally mercury lamps were used to do the selective hardening, which output 436 nanometre wavelength light. The sort you find in resin 3D printers, give or take, although they use LEDs, not mercury lamps, thank god. Later lamps produced shorter wavelengths at 365 nanometres, but between the fact that feature sizes were getting to be that size, and the need for higher throughput (ie more wafers made faster), the industry was looking for a better alternative. 1982 brought the solution – from IBM – which was using an excimer laser. Excimer lasers use an inert and reactive gas under high pressure and voltage to emit deep ultraviolet light – hence this process and class of machines being known as DUV. The two most common lasers in DUV machines are KrF – krypton fluoride – which outputs 248 nanometre light – and ArF – argon fluoride – which outputs 193nm light. Amazingly, we’ve been able to use much larger wavelengths of light than the feature size – that 193nm light can, in the right circumstances, make all the way down to 7 nanometre features. That’s in part thanks to a whole bunch of clever tricks, like immersing the wafer in pure water to change the index of refraction allowing for higher numerical aperture lenses – we’ll come back to what the hell that means shortly, don’t worry.

This is also where ASML comes into the picture. ASML was a spin-off of Philips, as ASM Lithography, in 1984, just after the introduction of deep ultraviolet techniques. They started creating photolithography machines, with their PAS 5500 platform being their first big success. Initially it used the “i-line” mercury lamps (the 365 nanometre one), but was upgraded with KrF and ArF lasers too. They went public in 1988 and by 2002 they were the world’s largest supplier of photolithography machines. In 1997 though they started researching ways to create and utilise extreme ultraviolet light – in the 10 to 30 nanometre range. To say there were challenges in creating these EUV machines would be an understatement. Extreme ultraviolet light like this is absorbed by almost anything, meaning the whole system needs to be under vacuum. The mirrors that are used to direct and control that light need to be extremely precise too, hence why Zeiss makes them. German precision and all, right? These are the flattest surfaces in the world, and they need to be to actually bounce the EUV rather than absorb it. The most insane part though is how ASML makes that 13.5 nanometre light though. See it turns out that if you explode a drop of molten tin with an extremely powerful laser, the resulting explosion happens to release 13.5nm wavelength photons. Science man, it’s barbaric magic sometimes. It took ASML over a decade to make their first production machine, shipping a prototype in 2010, and evolving the designs over the 2010s. 

Interestingly, in 2012, ASML decided to offer 25 percent ownership of themselves to their biggest customers as part of their “Customer Co-Investment Program”, with Intel taking 15 percent for a total of $4.1 billion (including just under a billion of R&D funding), TSMC took another 5% and Samsung took 3%. Interestingly Samsung eventually sold off their share, supposedly netting an 8x return on their investment. Not bad, huh? As far as I’m aware, both TSMC and Intel still own their shares in full. What’s even more interesting to me is that Intel stuck with DUV until mid 2022, with Intel 4 being the first process node to use ASML’s EUV machines. All of those 14nm+++++++ nodes, the 10 nanometre nodes that never really came to fruition, all of that was with DUV. That’s insane, and yet Intel have already started moving off of those EUV machines, onto ASML’s newest design, High NA EUV. High NA, or high numerical aperture (see, I told you we’d come back to that) machines capture more of that extreme ultraviolet light produced by vapourising tin droplets. The more light you capture, the less exposure time is needed, the more detailed the designs can be, and importantly you don’t need to do multiple exposures for a given design anymore. That means you can push out more wafers – ASML’s latest TWINSCAN EXE:5000 system can do 185 wafers per hour, or a little over 1.6 million wafers per year. It also has a resolution of just 8 nanometres, for up to 2 nanometre process nodes. These machines do cost a pretty penny though, with a DUV machine costing between $5 and 90 million, EUV is more like $220 million, and High NA is a whopping $400 million – and Intel has bought their entire 2024 stock. These machines are larger than a double decker bus, weigh more than a blue whale, and are under a total vacuum. These machines only further ASML’s total monopoly on the EUV market, with no other suppliers existing at all. 

You might be wondering what’s next – I mean a silicon atom is 0.2 nanometres wide, so you can only shrink feature size so far, and as you do you also run into issues like electron migration where an electron just jumps over the increasingly small gap without being let through by the gate – and it seems like the answer that’s increasingly being selected is gallium nitride, or GaN. You’ve likely heard of GaN in power electronics, like really efficient USB C power bricks that can push out 100W or more of power from what would traditionally be a pretty toasty 50 or 60 watt brick. The main reason for that is that GaN transistors can switch much faster and convert less of that energy into heat. Those benefits might make their way into logic circuitry too, with HRL Laboratories claiming to have made the first CMOS GaN transistor in 2016, theoretically providing more efficient, possibly faster clock speed, chips. We’ll have to wait and see on that one though!

So in short, ASML managed to take over the world of semiconductor manufacturing in just 40 years, and now with their new High NA machines are aiming to cement their place in all our pockets and PCs for decades to come. Basically all of your chips are made with ASML’s machines – be that DUV for the microcontrollers in your car or EUV for your CPU and GPU – and yet they’re an understated Dutch brand most haven’t heard of. It’s kind of incredible, and my god the fact we make EUV light by exploding tin is just… chef’s kiss madness.